TIE Plus

TIE-E Plus Contest Regulation

 

  1. General

The present document outlines the primary factors to consider prior to and after enrollment in the TIE-E Plus competition. We would kindly ask you to read it thoroughly and for any questions you may have that are not directly addressed in the following lines you can always reach up to us at tieplus@up-see.org, and one member in the organizing committee will get back to you as soon as possible. We are dedicated to ensuring your successful participation at the event and facilitating your up-skilling process within our virtual prototyping community.

  1. Brief description

TIE-E Plus Contest is a prestigious competition established by industry professionals in collaboration with academia, with the main goal of driving froward innovative practices in engineering education, particularly focused on product virtual prototyping methods and techniques.

Our objective is to help you understand current industry challenges and support you in becoming the engineer of tomorrow. We look to achieve this by exposing you to the latest technologies and industry product requirements. Thus, TIE-E Plus draws inspiration from real-life engineering challenges brought up by our industry partners and has as main goal to give you the chance to evaluate your engineering skill set against actual electronic product development challenges.

  1. Contestant profile requirements

The contestant must be enrolled at a higher education institution. Accepted profiles will fall under one of the following categories:

  • Undergraduate students
  • Graduate students
  • Master’s students
  • PhD Students

All applications will be verified by the organizing committee members. As soon as that happens you will get notified of the status of your application.
Besides that, the contestant shall have a minimum idea about the contest’s scope and show at least basic skills using the tools needed to solve the proposed subject.
Knowledge of English language (B1 level at least) is mandatory, as the subject presentation, trainings, and final report are/shall be written in English.

  1. Workflow

Further, a step-by-step guide for registering will be presented.

  1. First, identify the section you want to register to: Signal and Power Integrity, Thermal Management or Structural Analysis
  2. Fill in the registration form with the requested information.
  3. An acceptance or rejection notice will be sent to you.
  4. You will receive in your acceptance email the links to the specific group for your section. Please register and join the indicated group.
  5. During the solving period you’ll have access to a database of knowledge prepared by the technical committee members and a series of workshops. Feel free to join discussions and debates related to the subject.
  6. Solve the subject and create a report, considering the guidelines of each subject. Please remember that the quality of the report plays a major role in the evaluation.
  7. Upload the finished report and wait for our notification to see if you qualify to the next phase.
  8. Finalists will give a brief presentation on the 24th of April, live, in Sibiu, where they shall defend their approach, with arguments and examples, debating together with the committee.

Please be aware that the quality of your presentation plays a major role in the overall final evaluation. The preliminary results after the initial report analysis may change drastically after the final presentation.

We encourage collaboration and discussions with academic coordinators or other peers, yet we do not tolerate cheating. Do not upload a solution that was not developed by you, as we will find out later, during live presentations.

Good luck!

 

Contest Topics:

  • Signal Integrity (SI) – simulation for signal integrity associated with wired data transmissions at PCB and system level
  • Power Integrity (PI) – simulation for power supply distribution networks in high frequency digital applications

For more information we encourage you to access the following TIEplus pages:

 

TIEplus 2023 – Promotional Poster

TIE – E Plus  Steering Committee

TIEE Plus Committee

Chair:

Marcel MANOFU, Continental Automotive, Timişoara, Romania

Co-Chair:

Mihai DĂRĂBAN, Technical University of Cluj-Napoca

 Technical Committee – Academic Trainers

Chair: Mihai DĂRĂBAN, Technical University of Cluj-Napoca

Members:

Mădălin MOISE, POLITEHNICA of Bucharest

Daniela IONESCU, Gh. Asachi Technical University of Iaşi

Gheorghe PANĂ, Transilvania University of Braşov

Industrial Committee

Chair: Marcel MANOFU, Continental Automotive, Timişoara, Romania

Co-Chair: Radu VOINA, KEYTEK Innovation, Alba Iulia

 Members:

Cosmin MOISĂ, Continental Automotive, Timişoara

Cătălin NEGREA, Darknote Engineering

Mihai RUS, Continental Engineering Services

Andreea TASNADI, HUF Romania SRL

Roxana VLĂDUȚĂ, Marvell Technology

TIE – Eplus Past Editions Subjects

 

This page contains the TIE-Eplus subject for the past editions.

This will allow you to analyze the difficulty of the subjects and prepare for the upcoming TIE-Eplus challenges.

2023: The diagram below describes the simplified architecture of a System-on-Module PCB that is based on an ARM-Cortex SoC

The subject information for the TIE-Eplus 2023 edition is available in the PDF file below.

TIE-Eplus 2023 Subject

2020: Design the electrical connections within the Light-Control Engine and Picture-Projection of an Augmented Reality Headset System

The subject information for the TIE-Eplus 2020 edition is available in the PDF file below.

TIE-Eplus 2020 Subject

Full subject archive:

TIE-Eplus 2020 Subject archive

 

2019: Design of the power distribution network for the Image Sensor Board of a Space Cube Satellite PCB

The subject information for the TIE-Eplus 2019 edition is available in the PDF file below.

TIE-Eplus 2019 Subject

Full subject archive:

TIE-Eplus 2019 Subject archive

2018: Signal Integrity Analysis of a FPGA graphic accelerator card

The subject information for the TIE-Eplus 2018 edition is available in the PDF file below.

TIE-Eplus 2018 Subject

Full subject archive:

TIE-Eplus 2018 Subject archive

 

 

2017: Power Integrity Analysis of a DDR3 interface supply rail

The subject information for the TIE-Eplus 2017 edition is available in the PDF file below.

TIE-Eplus 2017 Subject

Full subject archive:

TIE-Eplus 2017 Subject archive

 

 

2015:Signal Integrity Analysis of a differential RSDS channel

The subject information for the TIE-Eplus 2015 edition is available in the PDF file below.

TIE-Eplus 2015 Subject

Full subject archive (with modeling information):

TIE-Eplus 2015 Subject archive

TIEplus 2021 – Promotional Poster

TIE+ Topics

 

The TIE+ subject of the 2021 edition will be focused on the simulation for signal and power integrity of electronic assemblies (single board and multi-board systems).

 

Topics for 2021 subject

This year’s subject will involve know-how from the following areas:

> Signal integrity simulation of differential transmission lines and LVDS channel requirements

> Definition of power distribution network requirements and design of decoupling network; typical power integrity simulation flow based on target impedance definition

> SPICE (or other circuit simulator) based thermal simulation using electro-thermal analogies; resistor network based thermal modeling

 

The need to incorporate such specialized electromagnetic simulations in to the PCB design flow is determined by the fact that, at high frequencies associated with digital data transmissions, the interconnect can be no longer considered an ideal electrical connection and the parasitic elements have to be taken in to consideration.

A general overview of the topics of interest for this disciplinary area is provided below.

> Transmission line theory
— Line impedance
— Propagation delay
— Reflections

> Single ended and differential data transmissions
— Terminations
— Eye diagrams
— Routing topologies

> Crosstalk
— Coupling mechanisms
— Near-End and Far-End crosstalk
— Crosstalk induced ISI

> IC modeling for SI simulations
— IBIS Modeling
— I\O buffer impedance analysis
— Package parasitics modeling

> Passive components & interconnect modeling
— S-parameters
— Touchstone modeling
— Capacitor modeling
— Via hole modeling
— 2D\3D Field solver extraction

> PCB Stack-up definition
— PCB material properties
— PCB build-up process
— Technology limitations
— IPC design recommendations

> Timing analysis
— Interface timing budget planning
— Interconnect propagation delays
— Jitter characterization

> Power Integrity of digital circuits
— Decoupling capacitor modeling
— Power nets/ plane parasitic modeling
— IR Drop Analysis
— Target Impedance definition for digital circuits
— AC domain analysis of decoupling networks
— Transient analysis of power line switching noise
— Power Distribution Network (PDN) Impedance analysis

> Signal and Power Integrity dependence

> Interconnect modeling techniques

> Electromagnetic field solvers

> Signal & Power Integrity simulations tools

> Thermal modeling
— Electro-thermal analogies
— Heat transfer basics: conduction / convection / radiation
— SPICE modeling of thermal circuits
— Compact modeling
— Steady state and transient simulation with compact models

Recommended Bibliography

— Signal Integrity Issues and Printed Circuit Board Design, Douglas Brooks, Prentice Hall PTR
— High-Speed Digital Design “A handbook of Black Magic”, H. W. Johnson, Prentice Hall PTR
— High-Speed Circuit Board Signal Integrity, Stephen C. Thierauf, Artech House
— Advanced Signal Integrity for High-Speed Digital Designs, Stephen Hall, Howard Heck,  IEEE-Wiley, 2009.
— Frequency Domain Characterization of Power Distribution Networks, Istvan Novak, Jason R. Miller, Artech House, Boston, 2007.
— Signal Integrity – Simplified, Eric Bogatin, Prentice Hall, New Jersey, 2004.
— Signal Integrity Characterization Techniques, Mike Resso, Eric Bogatin, IEC, 2009.
— Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages, Brian Young, Prentice Hall, 2000.
— Timing Analysis and Simulation for Signal Integrity Engineers, Greg Edlund, Prentice Hall, 2007.
— Principles of Power Integrity for PDN Design: Robust and Cost Effective Design for High Speed Digital Products, Larry D Smith, Eric Bogatin, Prentice Hall 2017
— Right the First Time: a Practical Handbook on High Speed Pcb and System Design, Lee W. Ritchey, John Zasio, Speeding Edge 2003
— Power Distribution Network Design Methodologies, Istvan Novak
— Frequency-domain Characterization of Power Distribution Networks, , Istvan Novak
— Thermal Design of Electronic Equipment, Ralph Remsburg
— A Heat Transfer Textbook, John H. Lienhard
— Thermal Considerations for Surface Mount Layouts, Texas Instruments application note
— Thermal Management Handbook for Electronic Assemblies, A. Krum J. Sergent,
— Power Integrity: Measuring, Optimizing and Troubleshooting Power Related Parameters in Electronics Systems, Steven M. Sandler

 

Simulation Tools                                                                                                                           

This is a list of the recommended simulation environments, which are widely used in the field of SI/PI simulations, however the usage of other simulation tools is not restricted. 

1. ANSYS EM Suite
    required applications: SI Wave, HFSS, DesignerSI = Electronics Desktop
    website: https://www.ansys.com/products/electronics/signal-integrity

   Training material: https://www.ansys.com/Resource-Library
   additional info:
   — a free trial is available upon request by your university coordinator
   — an extended series of training materials are available through the Customer Portal; contact your university coordinator  for login information
   — a set of ANSYS tutorials are available here 

2. Keysight ADS (Advanced Design System)
  website: http://www.keysight.com

  Required packages:
  — W2360EP SIPro Signal Integrity EM Analysis Element
  — W2359EP PIPro Power Integrity EM Analysis Element
  a full trial version is available online after registration

3. Hyperlynx (Mentor Graphics)
  required applications: Linesim (with PI capability), BoardSim; minimum version 8.1
  website: http://www.mentor.com/pcb/hyperlynx/

  Training material: http://www.mentor.com/white-papers

4. CST (Computer Simulation Technology)

  required applications:  Design Studio, PCB Studio, Microwave Studio; minimum version 2014
  website: www.cst.com

  Training material:
  https://www.cst.com/Events/webinars/Archive
  https://www.cst.com/Applications/Category/Signal+Integrity
  https://www.cst.com/Applications/Category/Power+Integrity

  additional info:
  — a free trial is available upon request by your university coordinator
 — the CST online webinar from the 6th of April / 2017 is available here

5. Allegro Sigrity (Cadence)
  required applications: Allegro Sigrity SI Base + Power Aware SI option
  website: http://www.cadence.com/products/sigrity/Allegro_Sigrity_SI_Base/pages/default.aspx

6. ALTERA PDN Design spreadsheet

  https://www.altera.com/support/support-resources/support-centers/signal-power-integrity/power-distribution-network.html

 

TIE+   Workflow & Timeline

 

Contest Timeline / 2021

  • 19 September: publication of the subject on website (brief description, text + figures)
  • 19 September – 30 September: registration of participants
  • 1 October: confirmation of acceptance
  • 4 October – 8 October: WEBINARS, TUTORIALS
  • 11 October: release of full subject details for the registered participants
  • 11 October – 20 October: solving of the subject
  • 20 October: uploading of the solutions (technical reports)
  • 21 October – 24 October: evaluation of the solutions by the technical committee
  • 25 October: Online session for presentation of the solutions by the contestants; announcement of the evaluation results (classification of contestants)

 

Registration Form

Support Ticket

All information related to contest including full subject and forum will be followed at http://eecamp.io.

Visit the website to download the Brief Subject Description

 

 

TIE+ Workflow

TIE+ will be organized based on an online platform where all the information exchange between contestants and committees will be managed.

 

On the 19th of September the subject will be published on the TIE+ page. This will allow willing contestants to analyze the difficulty of the subject and decide if they want to register or not.

 

There necessary registration steps for contestants are:

— Fill in the form containing basic information about the contestant’s education and relevant professional experience by latest 30th of September;
— The contestant profile will be analyzed by the technical committee and an approval/denial email response will be sent by 1st of October.
** the uploaded profile information must comply with the contestant profile requirements presented below, otherwise the profile will be automatically rejected.

 Between 4th and 8th of October a series of webinars will be held for the registered contestants. The presentation will be provided by the TIE technical committee members and simulation software representatives. Contestants will receive the WebEx invitations via the provided email address from the registration form.

 

Contestant Profile Requirements

The contestant must be registered within a higher education form :
— undergraduate student (accepting also graduates from 2021)
— master student
— PhD student

   By 11th of October all the contestants (with a validated profile) should have received the login information.

On the 11th of October the full set of data required to solve the subject will be published on the online platform. This marks the beginning of the “subject solving period” which will extend until 20th of October.

During this period the contestants will be able to communicate with the technical committee (ask question about the subject) by means of a dedicated forum with full visibility to all forum members.
* Communication between contestants during the subject solving period is strictly forbidden. Any striking resemblance between provided subject solutions will imply disqualification for all involved contestants.

Each contestant will go through the necessary simulation, design and documentation steps with the goal of delivering a technical solution to the proposed problem.

By 20th of October each contestant will upload the result of their work on solving the subject in the form of a technical report in *.pdf format.

   If the technical report is not uploaded by 20th of October (23:59 pm, GMT+2:00) the contestant is automatically disqualified.

   ANSYS and CST are providing free temporary licenses for TIE+ contestants.
Contact your university coordinator for details.

Technical Report Content
   The technical report should contain the following:
— exposure of the modeling approach for each circuit block including applicable details about field solver usage, port assignment, equivalent circuit definition
— simulation diagram/ electrical circuit for the entire system
— signal diagrams (time domain or frequency domain based on relevancy for the type of task) for the nets of interest
— signal parameter values that are relevant for the argumentation of the technical solution
(e.g impedance values of a line at a specified frequency)
— layout directives that are correlated with the simulation results (if they are clearly requested in the subject)
— summary of findings that define the proposed technical solution

After the technical report has been uploaded each contestant will receive an email from the technical committee confirming that the document was received and its content is adequate to be considered in the final evaluation process.
This email will also contain the invitation to the virtual evaluation meeting.
This year’s TIE+ evaluation session will be held over an online conference platform and each contestant will present the proposed solution.
This meeting will also feature discussions with the technical committee and announcement of the evaluation results (classification of the contestants).

The contestants are required to prepare a short presentation (20-25 min.) that will be exposed to the technical committee during an evaluation meeting. The presentation content must be in full agreement with the uploaded R&D report. The presentation support material can be either the technical report in *.pdf format or a PowerPoint presentation containing the relevant information for the work.

Each contestant will have to prove the usage of a simulation tool. During the evaluation session the technical committee might request simulation project files in order to prove the validity of the obtained results.

 

Evaluation of subject solutions

    The solution of the problem posed in the online subject, as a result of each contestant’s individual work during the days available between subject full data availability and solution submission deadline, will be uploaded in the form of a technical development report in *.pdf format.

 

Evaluation Criteria

 

> Modeling approach (using the right field solver for a specific problem)
> Modeling fidelity (how close does the simulation model gets to the physical system)
> Exposure of numerical results (e.g. variation timing parameters vs. trace length )
> Correctness of simulation problem formulation (transposing interface requirements and datasheet information in to a simulation environment )
> Formulation and argumentation of layout directives (clarity of directives)
> Applicability of the provided solution to PCB design (complies with generic IPC and is implementable using conventional fabrication processes)

 

Registration Form

 

 

SUBJECT 2020

 

Dear contestant,

The subject (brief version for informative purpose) for the TIEplus 2020 edition is available in the PDF file below.

TIEplus 2019 subject brief download [PDF] – available now!

This will allow you to analyze the difficulty of the subject and decide if you want to take on the challenge and proceed with the registration.

The necessary registration steps for contestants are:

> Fill in the form containing basic information about the contestant’s education and relevant professional experience by latest 17th of March (23:59, UTC+2 time zone);

> The contestant profile will be analyzed by the technical committee and an approval/denial email response will be sent by 18th of March. In case of participation approval this email will also contain the login information (username, password) to the online platform where all the relevant subject data will be published.

** the submitted profile information must comply with the contestant profile requirements presented below, otherwise the profile will be automatically rejected.

Registration Form

Contestant Profile Requirements

The contestant’s education level and\or professional experience must be within one of the following categories:

– undergraduate student
– master student
– PhD student
– Postdoctoral researcher

By 20th of March all the contestants (with a validated profile) should have received the login information.

Registration is opened until 17th of March (23:59, UTC+2 time zone).

On 20th of March the full set of data required to solve the subject will be published on the online platform. This marks the beginning of the “subject solving period” which will extend until 29th of March.

Submit a ticket to help you with any questions or problems that you may have

Support Ticket